NetSDR | Rf-Space
PC or TCP/IP controlled direct sampling SDR receiver. Frequency range 0.01-32 MHz all-mode, supports spectrum record/playback up to 1600 KHz bandwidth. Ideated in USA.
Reference market : ham-radio
|Frequency coverage||0.0100 ~ 32.0000 MHz |
|Modulation mode||CW / LSB / USB / AM / DSB / FM|
|Tuning step||1 Hz min|
|Sensitivity||CW||0.22 uV (10 MHz, 10dB S/N)|
|MDS (Minimum Detectable Signal)||-129 dBm (10 MHz)|
|A/D conversion||Freq.||80 Msps|
|Sampling out||12.5~2000 Ksps|
|RF attenuator||0 / 10 / 20 / 30 dB|
|Dynamic range||105 dB|
|Memory||Unlimited memory channels|
|Antenna||2 x BNC 50Ω connectors|
|Power supply||5 VDC external|
|Power consumption||1500 mA|
BNC (IF output)
BNC (10 MHz reference input)
|Mechanical and environmental data :|
|Operating temperature||from 0°C to +40°C|
|Dimensions||228 (W) x 38 (H) x 180 (D) mm|
 Usable up to 34 MHz
NetSDR is a high-performance apparatus suitable for connection via standard 100-base-T Ethernet network. The receiver uses an analog-to-digital converter (ADC) operating at 80 MHz with a resolution of 16 bits, dithering techniques ensure minimum spurious responses. The data processed by a digital down converter (DDC) made with an Xilinx FPGA extract the signals in I/Q format, ie in phase and quadrature, on a bandwidth selectable from the operator between 10 KHz and 1.6 MHz. This band acquired by the PC is managed by the SpectraVue and SDR-Radio software for filtering, demodulation and analysis functions. The software also allows the use of the receiver via Internet, the 1.6 MHz waterfall spectrogram as well as the demodulated audio can be transferred via a link. NetSDR uses the TCP/IP protocol and ethernet for all communications, this guarantees the widest functionality on PC, Mac and Linux systems. By networking the receiver can be placed remotely from the control point, multiple receivers can also be combined by setting a different IP address on the units.
The RF part of the electronics includes a series of attenuators, from zero to 30 dB, and a 10-section preselector which divides the frequency range into narrower segments of an octave. This solution reduces the load at the ADC input by optimizing the dynamic response in the presence of strong out-of-band signals. At the same time the very low phase noise of the master clock, -152 dBc/Hz @ 10 KHz offset at the test frequency of 15 MHz, keeps the value of the dynamics high even for signals of minimum spacing. Some hardware options relate to the clock oscillator with devices that further lower the phase noise. To mention the input for an external reference of 10 MHz, useful for applications that require a secure traceability in frequency stability.
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